learn-fpga, the tutorial to create @risc_v
cores such as #femtorv on #fpga is approaching 2K stars on github !
https://github.com/BrunoLevy/learn-fpga
Tomorrow, @risc_v
meeting at Inria Paris. I will be talking about the learn-fpga project (https://github.com/BrunoLevy/learn-fpga). Everyone can design his own RISC-V softcore on a FPGA, it is easy ! (no more than 200 lines of VERILOG for #femtorv)
#RISCV softcore #femtorv on #FPGA, using the LiteX system: design your own processor, plug-in SDRAM, framebuffer, SDCard, write some programs.
https://github.com/BrunoLevy/learn-fpga/blob/master/LiteX/README.md
Port of the 90's ST_NICCC demo (https://www.pouet.net/prod.php?which=1251), running on #femtorv risc-v core
(https://github.com/BrunoLevy/learn-fpga)
43/N
If you installed Yosys/NextPNR, generated a bitstream, made the little LEDs blink, then you are not that far away from a fully functional microprocessor. Am I joking ? Let me show you: this image is the complete VERILOG for #femtorv (200 lines).
Could be a great starting point for writing #femtorv episodes 3 (Zicsr) and episode 4 (virtual memory) for a full gentle continuous path from blinker to Unix-capable CPU.
Episodes 1 (minimalistic CPU) and 2 (pipelining) are here:
https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md
Help needed !
Amazing project by Michael Schröder: minimalistic Unix-like system on a minimalistic processor, in the spirit of #femtorv (but with interrupts and virtual memory !)
https://gitlab.com/x653/xv6-riscv-fpga
... and last but not least, it comes with a 3D-printable case with NeXT vibes, love it !
For more fun, you can add a $2 led matrix + MAX7219, and generate additional hardware to drive it. Then your #femtorv processor can say hello to you !