The massive Himbaechel-gowin backbone is already in decent condition and works on boards from #tangnano GW1N-1 already out of stock to the last one I have #tangprimer20k😉
It remains for me to implement a large piece of IO / IOLOGIC. Unfortunately it won't be photogenic - sort of like this TBUF check on the GW1NZ-1 Himbaechel-gowin. So I won't bother with the same blinking LEDs, but know that work is in full swing🙂
#fpga #apicula #sipeed #gowin

It's raining. The minimum task for today: to make a working IBUF on #tangnano1k, to do this I have to re-learn the programming of I/O banks and the fuses of the buffer itself.

#tangnano1k is faster to flash than plain #tangnano, so the turnover rate is higher 😉
#fpga #sipeed #apicula #gowin

#tangnano, tangnano1k, tangnano4k and tangnano9k passed the deserialization primitives test successfully.

I was expecting surprizes from 9k, but everything was fine.

Now one more board and the testing is done!

#apicula #gowin #sipeed #fpga

Here we go. Ports for all primitives from IDES4 to IDES10 are reassigned and work on #tangnano

Now I need to check on all available boards. I may have to do a couple of tricks for the GW1NR-9(C)😜

#apicula #fpga #gowin

The most important thing here is not unpacking the primitive itself, but the correct decoding of the wires leading to its FCLK port: the thing is that these are implicit wires, they are switched in a different place than where the IOs are and the choice of which wire the IO is connected to is not made by routing bits. mmm.. maybe that's a bit too much. Anyway, it's a pain in the ass and I'm glad I could decipher the images for the whole #tangnano family and GW1N-9
#fpga #apicula #gowin #sipeed

Check the operation of the OSER8 primitives on each of the possible #tangnano pins. This will take some time.

The input for the primitive is 8'b01011101 so asymmetric pattern.
#apicula #gowin

I swear this is the last video.

I added another primitive to #apicula, OVIDEO, which outputs consecutively 7 bits from parallel data. Of course, you can't get a nice blink here because of the odd number of bits and the wild division of frequency by 3.5

#tangnano #fpga #gowin

In the case of the OSER10 primitive (turns 10 parallel signals into a serial signal), diagnostics with LEDs is a madhouse - I keep losing count 🤣

#sipeed #tangnano #gowin #fpga #apicula

Gee!
#yosys -> #nextpnr ->#gowin-pack successfully build and code a PLL primitive for #gowin #tangnano.
The on-board quartz is 24MHz, the PLL generates ~72MHz

The bright segment is the LOCK signal, indicating that the PLL phases are synchronized.

This is a prototype, there are draconian restrictions on the range of parameters, a couple of supports and three or four questionable fuses. And there's still a lot of work to be done🙂
But this is truly a glorious day.🍾

#apicula #fpga

I2C display test. Yosys + nextpnr + gowin_pack.
It was actually a hard test of all the work in IOB area: switch to 3.3V from default 1.8V, program tri-state inout, switch to open-drain. 🎉😉

https://www.yrabbit.cyou/pub/fpga/yosys-2.mp4

#fpga #tangnano #yosys

Cute little display, this one with RGB and a different interface. It will still be second after the b/w OLED because I probably don't have enough #tangnano #fpga memory for a full screen color picture.

Gee, the new version of FPGA cell bit representation correctly recognized almost all kinds of I/O primitives (except TBUF)!
The old version also did this, but it was immediately wrong when I/O mode was changed to something other than the default and could not be cured.
I hope the new one will be more flexible.
#fpga #apycula #gowin #sipeed #tangnano

Gee, no differences detected!
Now I would have to deal with the corner elements, if it were not for the heat outside the window🙂
#fpga #tangnano

#fpga #TangNano
What is important here is not the incomplete adder itself, but how to assemble a circuit from several modules scattered across different files. I got it now😉

https://peertube.social/videos/watch/d3835c40-1c85-4495-8d02-834c3a7b62e6

First clock and 27bit counter! Do not pay attention to the glow of the segments except for the point --- a current of pull-up resistors flows through them, I was too lazy to turn them off🤣

https://peertube.social/videos/watch/5cce7758-7dcc-44a8-903b-a721a1bf5336

#fpga #TangNano