Aha! With #Aldec help, I've got Riviera-PRO running in Linux (Windows + WSL). I've got #gnuradio doing a Mode A transmission. I just need the final piece to connect the two and then I've got full cosimulation!

#sdr #fpga #vhdl

Well appears as if there's no concept of time in #gnuradio. Everything is sample based. It's understandable but means the first helper module I think I will need to write is a sample counter though to provide other modules with a concept of time.

#fpga #aldec #vhdl #riviera-pro

@Tathar Well, for avionics test, I do signal receipt and correlation and demodulation, then the other side modulation and transmission in #VHDL. However that's not what's making me walk through gnuradio. Apparently #Aldec has a block that lets you use #gnuradio in co-simulation with #Riviera-PRO. If I have an easier to work with signal generation or signal analysis tool, it would aid verification.

I've written signal toolbox stuff in VHDL for simulation, but I'll be honest, it's a pain in the ass to work with: tedious to construct and a pain in the ass to modify (depending on what you want.). There's a possibility gnuradio is easier (though also a possibility it is not. I've not yet got through a tutorial that actually gave me a sense of how the tool deals with time. I think it probably doesn't which means if I need a particular timing I will be sample counting and it'll make it anchored to sample rate when it'd just be nicer to wait X microseconds and then modulate.)

Progressing further through the #gnuradio tutorials. I'm not sure I"m yet to the point of knowing how to apply time based modulation to the signals, but possibly getting closer.

#sdr #fpga #aldec #riviera #vhdl

Playing around with GNU Radio, a software suite I had no idea existed until the other day. Apparently there's also (when I get more proficient with it) a way to pipe the output of this into Riviera-PRO for FPGA simulation. I have LONG wanted a better signal generation sandbox for verification and this could potentially be very neat. Just a lot of baby steps to learn it, it's a beast of a software and I need to be able to write modulation schemes for SIF, Mode S, et al

#sdr #vhdl #fpga #avionics #aldec #simulation

Finally got the #intel NCO core to properly sim in #aldec Riviera simulator. I really hate cores, especially encrypted ones.