For the clock, I will need to rewrite the constraints parser. I don't like writing parsers. I liked the #Forth parser until it came to floating point numbers and then the nightmare began.
I don't like to write parsers so on Monday I will read some article about C++, YACC and Lex. Because these things should be created automatically. #fpga #apicula

All right! Primitives using HCLK (OSER4/8/10/VIDEO IDES4/8/10/VIDEO) worked on #tangnano20k Himbaechel-#gowin. On the picture, just testing the last IVIDEO :)
#apicula #fpga #sipeed

If #riscv works on #tangnano20k, then simpler things will probably work. But I can't rely on luck, so I check everything. Here is the ELVDS 😃
#fpga #sipeed #apicula #gowin

Ladies and gentlemen, Himbaechel-#gowin supports #tangnano20k to the extent necessary for #riscv to function correctly (example attosoc). Hooray!
#apicula #sipeed #nextpnr #fpga

The last two tests worked on #tangnano1k, who is GW1NZ-1.
Now to the bath, and then make commits :)
#fpga #gowin #sipeed #apicula

I got the same good result with the vendor IDE and Himbaechel-#gowin with GW1NZ-1 using randomly selected pins. My theory is that it could still be power saving, but with dynamic control - so occupying a certain pin I inadvertently spoil the routing. It's very funny and interesting!
#gowin #apicula #fpga #sipeed

The list of goals no longer fits into the screen. Everything works except for #tangnano1k (GW1NZ-1), there seems to be some tricky mechanism here that I don't know about.
Like turning off some parts of the chip in order to save energy, but I would find such bits quickly enough, something a little different here. Intrigue!😀
#fpga #gowin #sipeed #apicula

Task for today: First pass of final testing: make sure every primitive on every board works and make final corrections if necessary. Then we repeat the process.🙂
#fpga #apicula #gowin #sipeed

This huge GW1NR-9 board, donated a hundred years ago by @pepijndevos , also learned #Riscv and searches for prime numbers. It has quartz twice as fast as the tangnano line, but only 4 LEDs.
It took to change the clock router and it's for the better😉
#fpga #gowin #apicula

And the obligatory check that #riscv still works :)
#fpga #apicula

Here I am a fool - I did not explicitly connect two of the three IDES16 primitive calibration inputs and could not achieve normal decryption all day!🤣

But in the end we have the final required primitive for the Himbaechel-#gowin architecture working properly!😀
#sipeed #apicula #fpga

Himbaechel #gowin found out what OSER16 is🎇
I hope to make IDES16 tomorrow and this, by the way, will be the last primitive, after which we can say that Himbaechel-gowin completely repeats the functionality of the generic version of gowin nextpnr.😉
#nextpnr #sipeed #apicula

I had to digress from 16-bit SERDES and implement an OSC primitive (unstable generator) of all kinds for all the chips I have.
So Himbaechel #gowin got an OSC out of the blue🤪
#fpga #apicula #sipeed #gowin

Himbaechel #gowin learned how to deserialize a 10-bit signal (IDES10).
At the top is the clock signal and input data, if they are multiples, then the output is beautiful :)
#fpga #sipeed #apicula

Himbaechel #gowin almost learned how to decode the serial signal using the IDES8 primitive.
Channel 0 is the slow clock, channel 1 is the input.
Why are the 2nd and 3rd channels always 0, you ask?
How glad I am that I remembered one feature before I tore out all the hair on my head - it is natural that in one cell you can place different deserialization primitives, but only one,
#fpga #apicula #sipeed

Himbaechel #gowin got OSER10 and OVIDEO primitives.
The second signal from the top should be 3.5 times slower than the first one, and someday some kind soul much smarter than me will tell me the divisor by 3.5 in Verilog.🙂
#sipeed #apicula #fpga

Yay! Himbaechel-gowin has taken the first step towards understanding high-speed clock I/O lines (HCLK)🤪
These are mostly implicit wires with a very funny distribution mechanism, it was interesting to figure it out.
#fpga #gowin #apicula #sipeed

I know that I promised, but every time I am surprised by the tricky things that work. Himbaechel-gowin has learned to use a differential output, as is usual on the entire line of chips at once😀
These LEDs are connected back-to-back, without GND, this is a "differential led"😜
#fpga #sipeed #gowin #apicula

The massive Himbaechel-gowin backbone is already in decent condition and works on boards from #tangnano GW1N-1 already out of stock to the last one I have #tangprimer20k😉
It remains for me to implement a large piece of IO / IOLOGIC. Unfortunately it won't be photogenic - sort of like this TBUF check on the GW1NZ-1 Himbaechel-gowin. So I won't bother with the same blinking LEDs, but know that work is in full swing🙂
#fpga #apicula #sipeed #gowin

Just.
How I check the next added feature - hundreds of images are generated with different arrangement of primitives and routing, and then they are flashed in a row and I have three seconds to evaluate if there are problems🤪
#fpga #apicula #sipeed #gowin