GW1NSR-4C Blinky, ladies and gentlemen!

This is a new board supported by #apycula!

#fpga #gowin #sipeed

Now that #apycula supports the GW1NS-4c I should solder these pins😀

https://freeradical.zone/@pepijndevos/107439191527640193

Yes, that's my bit!
Fuzzer working cell by cell simply could not detect such a thing, only a long contemplation of letters and numbers could.

Just kidding.
Now I need to generate new bases and do a bit by bit comparison. This is going to be a long time.
#gowin #fpga #apycula

Gee! It's hard to tell anything definite from this mishmash, but I see the spoon is there! 😀

This is a debug print + exploring vendor tables for the OPEN_DRAIN parameter of I/O blocks encoding.

#gowin #fpga #apycula

Gee, Gowin_V1.9.8 is almost friends with #apycula :)
#fpga

First run of all parts of the free toolchain for #gowin #fpga with ALU support. There were changes in #yosys (formal:) ), #nextpnr, #apycula.
My favorite example (shift) works on hw, I don't attach video, you've seen it a hundred times already.
But it's not worth releasing it into the wild while I see its weaknesses:)

No, the star segment is still not lit. This probably has nothing to do with packing different registers into the same slice, but I was hoping deep down that it would be fixed:)
#yosys #fpga #gowin #apycula

Check on the same bitstream (with different IO standards and combined different-type blocks in the same tile).
The extra input blocks disappeared, and this was not the goal, it turned out to be an unexpected side effect of the new bitfields storage structure.
This is a good thing😉
#gowin #apycula #fpga

ugh, the open collector flag turned out to be tied to I/O mode:(
If you speculate, it makes sense: other transistors must be used for a different voltage and hence switching to open collector mode is done by setting other bits.
I think that now I will check all flags at all possible I/O modes, it will significantly increase the time of base building, but at least I will be sure.
#fpga #apycula #gowin

Two buffers of different nature combined in one tile are recognized correctly!
This is fine. Although if #gowin just published the format of its bitstream...
# fpga #apycula

Gee, IOBs are recognized correctly regardless of the I/O standard! (A bunch of inputs on the left doesn't bother me yet) 😜
#fpga #apycula #gowin

Gee, the new version of FPGA cell bit representation correctly recognized almost all kinds of I/O primitives (except TBUF)!
The old version also did this, but it was immediately wrong when I/O mode was changed to something other than the default and could not be cured.
I hope the new one will be more flexible.
#fpga #apycula #gowin #sipeed #tangnano

So, the three-state buffers look good, let's do some diagnostics in the packer, and then I feel there will be some serious changes to the vendor bitstream unpacker.
(The video has nothing to do with the 3 state buffers, it's just a tease😜 )

#fpga #gowin #apycula

A little context: my joy is not in finding what lines to write in the constraints file, but in making changes to the free FPGA toolkit to (#nextpnr and #apycula) make it take those lines into account at all:)
Now all that's left is to find what I broke in the process:)