.@antmicro adapted the #OpenTitan configuration to fit into a small, accessible @XilinxInc #Artix7 A200T #FPGA, opening the path to synthesizing this #SystemVerilog design with the #opensource #Yosys/UHDM flow. Read more: https://riscv.org/blog/2023/04/adapting-opentitan-for-open-source-fpga-prototyping-and-tooling-development/ @google @chipsalliance
Original tweet : https://twitter.com/risc_v/status/1646134831858819072
#yosys #opensource #systemverilog #fpga #artix7 #opentitan