GCC 11.4 arrived today (Yay!)

Still find it strange that while GCC-11 added support for all the weird #AMX instructions, as well as a native flag for #SPR, there was never any support (original or backported) for the #FP16 instructions.

at time of posting the GCC website is still being updated, but this link should eventually link to the public docs: https://gcc.gnu.org/onlinedocs/gcc-11.4.0/gcc/

Experimenting with #FP16 in #Shaders

https://interplayoflight.wordpress.com/2022/12/30/experimenting-with-fp16-in-shaders/

Time for an #introduction!
I'm a young Canuck with interests/experience in #HPC, #Linux, #BLAS, #SYCL, #C, #AVX512, #Rust, heterogeneous compute & other such things.

Currently my personal projects are bringing #FP16 to the #OpenBLAS library, working to standardize what Complex domain BLAS FP16 kernels/implementations should look like, and making sure #SYCL is available everywhere.

I also write every now and again. Here's the tail of AVX512 FP16 on Alderlake
https://gist.github.com/FCLC/56e4b3f4a

Was going through the Risc-V Vector ISA spec (as you do) and noticed this little gem:

Specifically the line "When 16-bit and 128-bit element widths are added, they will be also be treated as IEEE-754/2008-compatible values. "

Unless I'm miss interpreting this, is Risc-V indicating future *native* support for 128 bit integer and floating point?

On the other hand, because I'm that guy: GOSH DARN IT, WHY NOT SHIP FP16 AS PART OF V.1 😭
https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf

#HPC #BLAS #RiscV #FP16 #ASM