New important bugfix release of the #openXC7 #opensource #FPGA toolchain.

https://github.com/openXC7/openXC7-snap/releases/tag/v0.5.1

Ich bin schon sehr enttäuscht von meinem #AnaloguePocket, ich habe bis heute nicht geschafft ein einziges #GameBoy #Game zu starten. Egal wie sehr ich die Sachen Reinige oder was auch immer ich mache, ich bekomme nur einen #Error Screen. Hat vielleicht jemand aus der #Tech
Ecke hier noch eine Idee für mich?

Achja: @ThreeM auch Radieren und 99%ISO hat nicht geholfen.

ich weiß nicht mehr weiter
#repair #löten #Elektrotechnik #fpga #retrogaming #retrogames #nintendo #analogue

Well Hi to everyone.
I went to Hamradio in 1989, professionnal RF engineer dc to 100GHz,System architect,french and swiss citizen.
I made a lot of contest from VHF to SHF in the past with the HB9WW team mainly in the 90's.
Linux user since 1993.
My tags
#linux #vuhshf #dsp #fpga #poweramplifier #openhw #contests #weaksignal #embeddedlinux

@BrunoLevy01 I have several #FPGA boards here. Three of them have an #ICE40 FPGA, three of them are Xilinx-based, and the last is the #ECP5 evaluation board with an ECP5-5G 85F. Which do you recommend for your FPGA tutorial series? Thank you!

After over a year and some refactoring, my #RISCV #FPGA Soft-CPU, written in VHDL, is up and blinking again.
Motivation is through the roof. Time to shitpost here a little, reuse this account.
TODO: (sort of) test RISC-V compliance, CSR-Registers, Interrupts, something something

I was curious how long it took to fully align the Xilinx/AMD CMAC core in simulation, so I generated and opened the example design. The simulation has been running in Vivado for 1.04ms of sim time and the rx_aligned flag still isn’t set.

I wish the documentation would state how long alignment should take in simulation with/without `define SIM_SPEED_UP, seems like a useful but missing piece of information. It’s also strange that it seems like SIM_SPEED_UP is actually required.
#FPGA
#AMD

IT'S ALL HAPPENING!

Open-source FPGA toolchain on macOS, in my good-friend-and-text-editor, Nova.

I'm still on the hunt for a better way (on a Mac) to synthesize SystemVerilog directly instead of converting it to Verilog first. If YOU know a way, lmkplskthx!

Nova is a fantastic, extensible tool from @cabel and his pals at @panic

#fpga #macDevelopment #yosys #verilog #systemVerilog #tangNano #panicNova #nova

Live now! Streaming for lolz. Let’s get some Analog Pocket coding on…

https://twitch.com/didiermalenfant

#ProjectFreedom #openFPGA #AnaloguePocket #FPGA #Verilog #IndieDev #GameDev #Twitch #Live

yosys users group - meet-up #002

September 7th at 18:00 CEST.

We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!

Afterwards we'll have time for your questions and suggestions.
Feel free to bring a friend!

Use this link to join:

https://meet.jit.si/NoisyAssembliesExpressEach

The YosysHQ team will be present and are looking forward to meeting you!

#yosys #fpga #meetup

Apparently there's at least one #FPGA board available in a 2280 m.2 form factor with PCIe. Now what would be the craziest use for such a thing...

ZX Next core has been updated for MiST :ablobcatenjoy:

= ZXN_230902.rbf =

- Update to the latest core (3.02)

#MiSTBoard #FPGA #ZXNext

https://github.com/mist-devel/mist-binaries/tree/master/cores/zxn

Just updated the FAQ on the whole logic, reg, bit, wire and var mess in #Verilog

I really wish I’d had that handy when I first started…

https://openfpgatutorials.org/docs/System-Verilog-FAQ

#OpenFPGA #FPGA #SystemVerilog #OpenFPGATutorials

Challenge: no IO for basic UART.
But we do have unused QSFP ports. With I2C for the eeprom... let's hack this SFP first.
#fpga

@guidoism It's all in the implementation. The projects I've mentioned have been designed to occupy a lot of real estate on an #FPGA. I'm looking forward to seeing how compact this #VLIW design will become, and if I can reduce the size footprint by an estimated two orders of magnitude.

@jangray We will see how long it takes for me to come back to SIMT. For now, something small that the community can toy with using the #ProjectIceStorm #ProjectTrellis ecosystem and related #FPGA hardware is my current goal. Thank you for your contribution.

I just made a small adjustment to the SNES emulator on the Analogue Pocket , so the NTSC "square pixels" mode will fill up the entire screen. On a black model, you can barely see the small letterbox, on a white one it looks so much better without.

#Analogue #AnaloguePocket #Retro #SNES #Gaming #FPGA

Une version fluorescente pour la console #AnaloguePocket #Retro #Gaming #FPGA https://arstechnica.com/gaming/2023/08/analogues-supercharged-modern-day-game-boy-now-glows-in-the-dark/

One of the first big insights from my #VLIW #GPU journey is the relative size of VLIW cores compared to a vector or SIMT implementation. If you look at the Vortex GPGPU from Georgia Tech, or the Nyuzi GPGPU from Jeff Bush, the core sizes of those projects encroach ~100,000 LUTs/logic elements. On the other hand, a VLIW-style core is closer to ~3000 LUTs/logic elements. This will hopefully enable a degree of rapid prototyping on #FPGA using open source tools.

Ars Technica: Analogue’s supercharged modern-day Game Boy now glows in the dark https://arstechnica.com/?p=1963785 #Tech #arstechnica #IT #Technology #nintendogameboy #analoguepocket #GameboyAdvance #nintendosnes #nintendones #retrogaming #openFPGA #retropie #GameBoy #Gaming #Tech #fpga

Analogue’s supercharged modern-day Game Boy now glows in the dark - Enlarge / The Analogue Editions: Pocket Glow console is $30 more expens... - https://arstechnica.com/?p=1963785 #nintendogameboy #analoguepocket #gameboyadvance #nintendosnes #nintendones #retrogaming #openfpga #retropie #gameboy #gaming #tech #fpga