Ok so it's still a bit buggy on windows, and ModelSim doesn't play nice.

But combined with #GHDL for open source #VHDL simulation and #gtkwave for wave viewing it's a surprisingly comfortable to set up tool chain, especially on Linux it's all just via package manager and pip~

Now to learn proper file structuring and documenting habits to raise the code quality bar a bit, probably add proper test benches~
Again #TerosHDL helps with built in docs generator <3

In case this this has baffled anyone else for years, under the Edit menu there's a Toggle Hier button and Set Max Heir button that do the trick on 3.3.104 #gtkwave #fpga #vcd #fst

Is there a way in gtkwave to have it display more of a signals hierarchy? In Modelsim you can have it show anywhere from none to the entirety, but I can't figure out how to do that in gtkwave. #fpga #gtkwave #vcd #fst

Why, #gtkwave, why? What don't you like? You see the values from the sim #fpga and you correctly know that they aren't 0. And you seem to know it's a string of bits. What does that leave? Why are you angry/confused by 1s and only in this variable?

#VHDL #techSupport

Anyone know how to convert a vcd to text file?

I'm trying to verify my vhdl program with a python version (which saves the output to a text file), but the best i can seem to get out of #modelsim to a file is VCD.

I would like to write my own testbenches, simulate with #ghdl and then view output with #gtkwave but until I can actually figure out how to write a testbench I'm stuck with #modelsim and quartus prime :(