YRabbit · @yrabbit
188 followers · 5291 posts · Server mastodon.sdf.org

Ladies and gentlemen, Himbaechel- supports to the extent necessary for to function correctly (example attosoc). Hooray!

#GoWin #tangnano20k #riscv #apicula #sipeed #nextpnr #fpga

Last updated 1 year ago

YRabbit · @yrabbit
180 followers · 5252 posts · Server mastodon.sdf.org

Himbaechel found out what OSER16 is🎇
I hope to make IDES16 tomorrow and this, by the way, will be the last primitive, after which we can say that Himbaechel-gowin completely repeats the functionality of the generic version of gowin nextpnr.😉

#GoWin #nextpnr #sipeed #apicula

Last updated 1 year ago

YRabbit · @yrabbit
189 followers · 5204 posts · Server mastodon.sdf.org

Himbaechel P&R architecture for chips has learned how to handle the part of the IO needed to run a VGA display. The frequencies are generated using a PLL.😉

#GoWin #sipeed #apicula #nextpnr #fpga

Last updated 1 year ago

YRabbit · @yrabbit
188 followers · 5190 posts · Server mastodon.sdf.org

So for the Himbaechel I need chip pins and delays.

Haven't decided what to tackle first, maybe go pick currants yet😜

#GoWin #fpga #apicula #nextpnr

Last updated 1 year ago

YRabbit · @yrabbit
187 followers · 5172 posts · Server mastodon.sdf.org

yay!
Himbaechel-gowin got a memory! Not block-based, regular LUT-based. Lucky day, tomorrow I have to check how this thing works😉

#GoWin #sipeed #nextpnr #apicula #fpga

Last updated 1 year ago

YRabbit · @yrabbit
187 followers · 5172 posts · Server mastodon.sdf.org

ALU appeared on Himbaechel !

I need to check different cases.

#GoWin #fpga #sipeed #apicula #nextpnr

Last updated 1 year ago

Computer Engineering JMU · @ce
6 followers · 7 posts · Server mastodon.acm.org

@phf @yosyshq this is the upduino v1 board with (there is even a v3) HW Description (mainly a I2C controller) is done in and synthesis with and it’s ghdl plugin. Place and route is done with . Picture shows floorplan and utilization.

#lattice #ice40 #ghdl #yosys #nextpnr #fpga

Last updated 1 year ago

YRabbit · @yrabbit
185 followers · 5163 posts · Server mastodon.sdf.org

Himbaechel for gowin now has support for wideluts!🤪

#GoWin #sipeed #apicula #nextpnr #fpga

Last updated 1 year ago

YRabbit · @yrabbit
184 followers · 5154 posts · Server mastodon.sdf.org

Himbaechel-gowin has learned how to work with all types of flip-flops and can now show a typical "shift" example!

#GoWin #sipeed #fpga #apicula #nextpnr

Last updated 1 year ago

YRabbit · @yrabbit
179 followers · 5048 posts · Server mastodon.sdf.org

So let's generate two hundred images for by changing the "--seed" parameter and then add the problematic wires and generate two hundred more images.

I hope that at least one couple hundred will show stable operation on the hardware.

#fpga #nextpnr #apicula #GoWin

Last updated 1 year ago

· @mole99
26 followers · 32 posts · Server fosstodon.org

@yrabbit
Very exciting! But please take your time with everything, I will be happy to try it out once it's ready 😃️

By the way, I would be very interested in your thought process and the steps involved in implementing a new primitive like ELVDS in + + .
Maybe someday you could toot about this in detail?

#apicula #yosys #nextpnr

Last updated 1 year ago

YRabbit · @yrabbit
168 followers · 4867 posts · Server mastodon.sdf.org

Now OSER16 goes through the whole chain -> -> , a binary image is generated and ... doesn't work🤣

Time to look for some tricks.

#yosys #nextpnr #apicula #fpga

Last updated 2 years ago

YRabbit · @yrabbit
167 followers · 4864 posts · Server mastodon.sdf.org

OSER16
Generating chip bases, going through synthesis and placing/rooting😀
Of course, the funniest thing isn't there yet - bit filling - and nothing works. And also about a gazillion correctness checks are missing, but it's a start!

#yosys #nextpnr #fpga #apicula #GoWin #sipeed

Last updated 2 years ago

YRabbit · @yrabbit
164 followers · 4838 posts · Server mastodon.sdf.org

Yes, IDES4/8/10/video all use different circuits for the output wires, and everything changes at once: q[0] is different for each.

I can see the pattern, but I'll have to change the a bit

#nextpnr #fpga #apicula #GoWin

Last updated 2 years ago

· @talpa
14 followers · 176 posts · Server fosstodon.org

Surprisingly how enjoyable it is to write a serial port (for the second time) in .
This time intended to be synchronous to the "sysclk".
It sure makes it easier to stick with just one clock domain :)
And yes I know that this will probably be the millionth time any one has written an uart.

Also if you like FPGAs go checkout and they are amazing projects

#verilog #yosys #nextpnr

Last updated 2 years ago

· @talpa
13 followers · 171 posts · Server fosstodon.org

Also incredible how much better they feel than the closed source programs (granted I have only tried Xilinx, but holly GB-atman that is a large software package, also sure is annoying to renew there stupid license)

#yosys #nextpnr

Last updated 2 years ago

YRabbit · @yrabbit
152 followers · 4591 posts · Server mastodon.sdf.org

Yes, that 49th parameter turned out to be exactly the problem area. In addition, its fuses were not in the PLL cell, but in one of the corner blocks.
It was funny, it took a lot of changes to and the packer, but the signal was received.

I'm satisfied, I really like looking for patterns in numbers, and I have trouble writing a couple of lines in verilog🤣

#nextpnr #GoWin #fpga #apicula

Last updated 2 years ago

YRabbit · @yrabbit
148 followers · 4547 posts · Server mastodon.sdf.org

It has just come to my attention that the vendor IDE has a VGA example as part of it.
So I just took it and compiled ->->

And marvel: no difference! The example uses PLL and it's the same source code! (well, except for two unimportant lines, and it's not my fault - I know exactly how to code these ports, but I need to change )

#yosys #nextpnr #apicula #fpga

Last updated 2 years ago

YRabbit · @yrabbit
147 followers · 4510 posts · Server mastodon.sdf.org

It snowed all day and it was good for productivity: not only did I describe the connections of the first big MUXa to the pins in , but I did the same with the second one:)

#nextpnr #fpga

Last updated 2 years ago

Benoît Allard · @benallard
5 followers · 11 posts · Server osna.social

There is this game , it’s about solving logic in a very tactile way: literally with balls and switches. Well, it‘s first about , and then -n-routing the pieces on the board. See where I’m aiming at? We do actually have tools that do that very well! What‘s needed is *just* defining our board and it’s components in a formal way to be compatible with and . Then we will be able to express any as a Turing-tumble board. Yeah!

#TuringTumble #puzzles #synthesising #place #yosys #nextpnr #verilog

Last updated 2 years ago