Ladies and gentlemen, Himbaechel-#gowin supports #tangnano20k to the extent necessary for #riscv to function correctly (example attosoc). Hooray!
#apicula #sipeed #nextpnr #fpga

Himbaechel #gowin found out what OSER16 is🎇
I hope to make IDES16 tomorrow and this, by the way, will be the last primitive, after which we can say that Himbaechel-gowin completely repeats the functionality of the generic version of gowin nextpnr.😉
#nextpnr #sipeed #apicula

Himbaechel P&R architecture for #gowin chips has learned how to handle the part of the IO needed to run a VGA display. The frequencies are generated using a PLL.😉

#sipeed #apicula #nextpnr #fpga

So for the Himbaechel #gowin I need chip pins and delays.

Haven't decided what to tackle first, maybe go pick currants yet😜

#fpga #apicula #nextpnr

yay!
Himbaechel-gowin got a memory! Not block-based, regular LUT-based. Lucky day, tomorrow I have to check how this thing works😉
#gowin #sipeed #nextpnr #apicula #fpga

ALU appeared on Himbaechel #gowin !

I need to check different cases.

#fpga #sipeed #apicula #nextpnr

@phf @yosyshq this is the upduino v1 board with #Lattice #ice40 (there is even a v3) HW Description (mainly a I2C controller) is done in #GHDL and synthesis with #yosys and it’s ghdl plugin. Place and route is done with #nextpnr. Picture shows #FPGA floorplan and utilization.

Himbaechel for gowin now has support for wideluts!🤪

#gowin #sipeed #apicula #nextpnr #fpga

Himbaechel-gowin has learned how to work with all types of flip-flops and can now show a typical "shift" example!

#gowin #sipeed #fpga #apicula #nextpnr

So let's generate two hundred images for #fpga by changing the "--seed" parameter #nextpnr and then add the problematic wires and generate two hundred more images.

I hope that at least one couple hundred will show stable operation on the hardware.

#apicula #gowin

@yrabbit
Very exciting! But please take your time with everything, I will be happy to try it out once it's ready 😃️

By the way, I would be very interested in your thought process and the steps involved in implementing a new primitive like ELVDS in #apicula + #yosys + #nextpnr .
Maybe someday you could toot about this in detail?

Now OSER16 goes through the whole chain #yosys -> #nextpnr -> #apicula, a binary image is generated and ... doesn't work🤣

Time to look for some tricks.
#fpga

OSER16
Generating chip bases, going through #yosys synthesis and #nextpnr placing/rooting😀
Of course, the funniest thing isn't there yet - bit filling - and nothing works. And also about a gazillion correctness checks are missing, but it's a start!
#fpga #apicula #gowin #sipeed

Yes, IDES4/8/10/video all use different circuits for the output wires, and everything changes at once: q[0] is different for each.

I can see the pattern, but I'll have to change the #nextpnr a bit

#fpga #apicula #gowin

Surprisingly how enjoyable it is to write a serial port (for the second time) in #verilog.
This time intended to be synchronous to the "sysclk".
It sure makes it easier to stick with just one clock domain :)
And yes I know that this will probably be the millionth time any one has written an uart.

Also if you like FPGAs go checkout #yosys and #nextpnr they are amazing projects

Also incredible how much better they feel than the closed source programs (granted I have only tried Xilinx, but holly GB-atman that is a large software package, also sure is annoying to renew there stupid license)

#yosys #nextpnr

Yes, that 49th parameter turned out to be exactly the problem area. In addition, its fuses were not in the PLL cell, but in one of the corner blocks.
It was funny, it took a lot of changes to #nextpnr and the packer, but the signal was received.

I'm satisfied, I really like looking for patterns in numbers, and I have trouble writing a couple of lines in verilog🤣
#gowin #fpga #apicula

It has just come to my attention that the vendor IDE has a VGA example as part of it.
So I just took it and compiled #yosys->#nextpnr->#apicula

And marvel: no difference! The example uses PLL and it's the same source code! (well, except for two unimportant lines, and it's not my fault - I know exactly how to code these ports, but I need to change #yosys)
#fpga

It snowed all day and it was good for productivity: not only did I describe the connections of the first big MUXa to the pins in #nextpnr, but I did the same with the second one:)
#fpga

There is this game #TuringTumble, it’s about solving logic #puzzles in a very tactile way: literally with balls and switches. Well, it‘s first about #synthesising, and then #place-n-routing the pieces on the board. See where I’m aiming at? We do actually have tools that do that very well! What‘s needed is *just* defining our board and it’s components in a formal way to be compatible with #yosys and #nextpnr. Then we will be able to express any #verilog as a Turing-tumble board. Yeah!