RISC-V · @risc_v
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RT from Cobham Gaisler (@cobhamgaisler)

Jan Andersson, Director of Engineering, presented our NOEL-V processor IP core and our radhard GR765 and GR7xV devices currently in development at the RISC-V in Space Workshop at @esa. Our future radhard products will also implement the @risc_v ISA.

Original tweet : twitter.com/cobhamgaisler/stat

#gr7xv #gr765 #noelv #riscv

Last updated 2 years ago

Now Cobham&Gaisler speak about their CPU which is and 7-stage. Best: there is a version in GitHub to play and test for homepurpose (language is VHDL)

#noelv #riscv #ipsoc22 #semiconductor

Last updated 2 years ago