Didier Malenfant :analogue: · @didier
485 followers · 339 posts · Server malenfant.netJust updated the FAQ on the whole logic, reg, bit, wire and var mess in #Verilog
I really wish I’d had that handy when I first started…
#verilog #openfpga #fpga #systemverilog #openfpgatutorials
Last updated 1 year ago