yosys users group - meet-up #002

September 7th at 18:00 CEST.

We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!

Afterwards we'll have time for your questions and suggestions.
Feel free to bring a friend!

Use this link to join:

https://meet.jit.si/NoisyAssembliesExpressEach

The YosysHQ team will be present and are looking forward to meeting you!

#yosys #fpga #meetup

There's an RTL-to-GDS toolchain for unattended chip build, called #OpenLane:
https://github.com/efabless/openlane#overview

"OpenLane is an automated RTL to #GDSII flow based on several components including #OpenRoad, #Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. The flow performs full #ASIC implementation steps from RTL all the way down to GDSII"

See also the videos from #FOSSI
https://www.youtube.com/watch?v=EczW2IWdnOM

@theruran @cstanhope
@niconiconi

I recently came across Princeton's Reconfigurable Gate Array but I can't quite figure it out. I think perhaps it's a story for architecting FPGAs and then evaluating the architectures. Fabrication might not be part of the story - although maybe any foundry would do. Maybe a project for Google's Free Chips offer (see #skywater, #openlane)??

https://prga.readthedocs.io/en/latest/

skywater:
https://news.ycombinator.com/item?id=23755693

@vertigo