YosysHQ · @yosyshq
434 followers · 39 posts · Server fosstodon.org

yosys users group - meet-up #002

September 7th at 18:00 CEST.

We'll start with a demo of our new formal equivalence checker targetting the flow. Bring your own design to follow along!

Afterwards we'll have time for your questions and suggestions.
Feel free to bring a friend!

Use this link to join:

meet.jit.si/NoisyAssembliesExp

The YosysHQ team will be present and are looking forward to meeting you!

#openlane #asic #yosys #fpga #meetup

Last updated 1 year ago

Ed S · @EdS
481 followers · 3264 posts · Server mastodon.sdf.org

There's an RTL-to-GDS toolchain for unattended chip build, called :
github.com/efabless/openlane#o

"OpenLane is an automated RTL to flow based on several components including , , Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. The flow performs full implementation steps from RTL all the way down to GDSII"

See also the videos from
youtube.com/watch?v=EczW2IWdnO

@theruran @cstanhope
@niconiconi

#openlane #GDSII #OpenRoad #yosys #asic #fossi

Last updated 2 years ago

Ed S · @EdS
483 followers · 3266 posts · Server mastodon.sdf.org

I recently came across Princeton's Reconfigurable Gate Array but I can't quite figure it out. I think perhaps it's a story for architecting FPGAs and then evaluating the architectures. Fabrication might not be part of the story - although maybe any foundry would do. Maybe a project for Google's Free Chips offer (see , )??

prga.readthedocs.io/en/latest/

skywater:
news.ycombinator.com/item?id=2

@vertigo

#skywater #openlane

Last updated 4 years ago