RISC-V chip designer SiFive previews upcoming P870 series CPU cores with speeds up to 3 GHz, shared L2 cache, and support for heterogenous architecture (they can be paired with lower-performance cores). https://www.servethehome.com/sifive-p870-risc-v-processor-at-hot-chips-2023/ #SiFive #chips #RiscV #SiFiveP870
#sifive #chips #riscv #sifivep870
Our engineers Lawrence Hunter and Kiran Ostrolenk by the poster showing the work done to add support for #RISC-V vector cryptography extensions to #QEMU. Thanks #SiFive for sponsoring this work!
We wrote a blog post about it here: https://www.codethink.co.uk/articles/2023/vcrypto_qemu/
#risc #qemu #sifive #riscvsummiteurope
In the talk "#Android on #RISCV" at #RISCVSummitEurope, we spotted a reference to the work we did in collaboration with #SiFive on supporting RISC-V's vector cryptography in #QEMU. Nice to see!
We wrote an article on the project here:
#android #riscv #riscvsummiteurope #sifive #qemu
"This almost-great Raspberry Pi alternative is missing one key feature" Dude, I'll tell you what the key feature is that's missing. The missing feature is identical ports and pinout. Why is this so hard for Raspberry Pi competitors to comprehend? So many unused alternative boards out there, so many unused Raspberry Pi accessories. The solution is straightforward, no? #RaspberryPi #Radxa #BananaPi #Pine64 #Sipeed #SiFive https://www.zdnet.com/home-and-office/this-almost-great-raspberry-pi-alternative-is-missing-one-key-feature/
#raspberrypi #radxa #bananapi #pine64 #sipeed #sifive
Finally, I've created a #RISC-V #Assembly code which works! https://gitlab.com/vazhnov/native-blink_asm_sparkfun_red-v_thing_plus/-/blob/main/Blink-all-GPIO_asm/src/gpio.S
Thanks to #PlatformIO, #SiFive and #SparkFun.
#sparkfun #sifive #platformio #assembly #risc
Saturday Morning Board Club today replaced the #SiFive HiFive1b test board in TinyHCI with clean new wire wrapped one. #tinygo #riscv #hardwareci
#hardwareci #riscv #tinygo #sifive
RT from Arteris IP (@arteris_noc)
@arteris_noc and @SiFive partner to provide a greater choice of integrated and optimized solutions with leading @SiFive RISC-V processor IP and @arteris_noc system IP. Read the release. https://www.arteris.com/press-releases/arteris-sifive-risc-v-soc-design-edge-ai-applications?hss_channel=tw-197373651
#semiconductor #innovation #soc #noc #risc-v #SiFive #Arteris
Original tweet : https://twitter.com/arteris_noc/status/1630320619165196288
#arteris #sifive #risc #NOC #soc #innovation #semiconductor
As goes radation-hardened SoCs, so goes a segment the #embedded computer industry. I worked on the #VxWorks #RTOS port for PPC750+7400, the basis of #RAD750, and that was a major performance bump. The #SiFive X280 should enable a huge bump in smart on board processing for spacecraft. #riscv #powerpc
SiFive RISC-V cores and Microchip processors will power NASA's future space missions | TechSpot
https://www.techspot.com/news/95911-sifive-risc-v-cores-microchip-processors-power-nasa.html
#embedded #vxworks #rtos #rad750 #sifive #riscv #powerpc
SiFive HiFive Pro P550 : une carte mère RISC-V équipée par Intel
Disponible au printemps prochain, la carte mère SiFive HiFive Pro P550 sera équipée d'un SoC RISC-V "Horse Creek" d'Intel.
https://www.minimachines.net/actu/sifive-hifive-pro-p550-115694
#actu #intel #risc #sifive #minimachines
Pare che quest'estate uscirà una scheda di sviluppo #RISCV a 7nm sviluppata da #Intel e #SiFive.
La cosa più interessante è vedere come anche Intel stia cercando una via oltre x86. Con l'orientamento verso #ARM del mercato consumer, l'ancora valida concorrenza di Intel sull'x86 e il germogliare di Risc-V, #AMD rimarrà con il cerino della architettura x86 in mano?
#riscv #intel #sifive #arm #amd
SiFive HiFive Pro P550 dev board coming this summer with Intel "Horse Creek" RISC-V chip
#horsecreek #riscv #intel #sifive #devboard #hifiveprop550
Funny... I was wondering what happed to the RISC-V movement of a few years ago, and #SiFive the org.
The #VisionFive #StarFive as well as the #Pine64 #Star64 are both using the same 28nm RISC-V process that the #SiFive HiFive Unleashed used.
So, at best, expect quad core, 1.5GHz performance, not the bleeding edge.
More in the lines of engineering samples than what the #AlphaWave #ZeusCORE is professing to be with TSMC's 3nm process.
#VisionFive #StarFive #pine64 #star64 #sifive #alphawave #zeuscore #riscv
Just got my @thepine64 Soldering Iron Pinecil V2. Amazing power in such tiny form-factor. And it controlled with @risc_v RV32IMAFC RISC-V #SiFive E24 Core
@geert @dougli1sqrd@pixelfed.social @erikalegernes
The little #riscv CPU there is the #hifive from #sifive. It's fast at max 450 MHz, but only has 16k of memory 😱! So that was the smallest frame buffer I could fit inside the chip memory.
I'm still sending each real pixel line, but I repeat the same line 5x or whatever, and each pixel lasts for 4 real pixels.
RT from Golem.de (@golem)
CPU: #Sifive erweitert schnellsten RISC-V-Kern um Vektor-ALU #RISCV https://glm.io/169415?s
Original tweet : https://twitter.com/golem/status/1587741661420978176
RT from DIGITIMES Asia (@DIGITIMESAsia)
SiFive releases high-performance processors for small-size, high-volume applications #RISCV #SiFive #wearable #DIGITIMES https://www.digitimes.com/news/a20221102PR200.html
Original tweet : https://twitter.com/DIGITIMESAsia/status/1587765180632399872
#riscv #sifive #wearable #digitimes