@sassageflare well, that's why I I'd use a #PCIe "#Sideplane" [#Backplane] because this way one can freely choose between #amd64 / #ARM64, #SPARCv9, #ppc64 and #riscv64 for their Host System....
But admittedly, modern high-end systems are kinda "boring"...
https://www.youtube.com/watch?v=gT59YOdch8M
#riscv64 #ppc64 #sparcv9 #arm64 #amd64 #backplane #sideplane #pcie
@ted_dunning @profoundlynerdy @Houl the only.asvantage is that #SPARCv9 & #POWER9 are #FLOSS'd like #RISCV so the limiting factor would be economies of scale and the ability to procure fabbing, which sadly isn't #FLOSS'd yet ( #LibreSilicon works on that!)...
This literally bit #Russia in the rear as #TSMC canceled any deliveries for #MCST's chips they fabbed on 28nm nodes...
#MCST #TSMC #Russia #libresilicon #riscv #FLOSS #power9 #sparcv9
@malwaretech This is worse than the shit #MCST is spitting out...
they are at least aware that their tech is reused 28nn TSMC with #SparcV9
https://en.wikipedia.org/wiki/MCST