A pet project I'm working on right now is system-lisp, a #lisp dialect for hardware design, verification and virtual prototyping. It is meant to be a lisp-like alternative to #Verilog #SystemVerilog #VHDL #SystemC and Specman e. It will support digital, analog and mixed signal simulation as well as formal verification for digital designs and digital synthesis. You'll be able to design, simulate and verify your own hardware devices that can range from simple circuits, gadgets, appliances, cars planes or even spaceships. Right now I'm working on the discrete event simulation engine. I'm implementing it in #commonlisp but I intend to make it backend agnostic in the future so that it can also run on top of #scheme or other Lisp dialects. For more updates follow #systemlisp. Wish me luck.

[#Actu] « Verilator 4.002 » https://linuxfr.org/news/verilator-4-002 #Matériel #systemc #verilog #c++