Gray Beard · @graybeard85
13 followers · 88 posts · Server universeodon.com

now supports signals, these are objects whose values change over time and which emit posedge, negedge and edge events. In the picture below is a small example with some clock dividers. Still not ready to publish on github. Will do so when I'll have an asdf-able cl package and some interesting simulation examples. Next I will add support for exporting vcd waveform files and data types to 2-value and 4-value logic signals.

#systemlisp #eda #verilog #vhdl #systemverilog #lisp #commonlisp

Last updated 2 years ago

Gray Beard · @graybeard85
13 followers · 88 posts · Server universeodon.com

now supports synchronization events. Next, I'll add support for signals. It's starting to take shape. Soon it will become a minimalistic HDL and I'll start implementing and simulating simple designs and testbenches with it. Stay tuned!

#systemlisp #lisp #commonlisp #verilog #vhdl #eda

Last updated 3 years ago

Gray Beard · @graybeard85
13 followers · 88 posts · Server universeodon.com

can simulate time! Next up, I'll add support for events, signals and expressions of signals. Moving forward slowly but steady. Will soon publish on github.

#systemlisp #lisp #commonlisp #eda

Last updated 3 years ago

Gray Beard · @graybeard85
0 followers · 4 posts · Server mstdn.social

Hello fellow Mastodonians! A few things about myself, I've worked most of my career in the semiconductor industry. I'm an expert in pre-silicon functional hardware verification using combined with other languages for higher level modeling such as . Right now I'm looking into to develop an EDA tool called . I'm also interested in and . Big fan of Civilization 3 and Spaceflight Simulator games.

#astrodynamics #geopolitics #systemlisp #commonlisp #Python #matlab #cpp #uvm #systemverilog #Introduction

Last updated 3 years ago

Gray Beard · @graybeard85
2 followers · 35 posts · Server universeodon.com

A pet project I'm working on right now is system-lisp, a dialect for hardware design, verification and virtual prototyping. It is meant to be a lisp-like alternative to and Specman e. It will support digital, analog and mixed signal simulation as well as formal verification for digital designs and digital synthesis. You'll be able to design, simulate and verify your own hardware devices that can range from simple circuits, gadgets, appliances, cars planes or even spaceships. Right now I'm working on the discrete event simulation engine. I'm implementing it in but I intend to make it backend agnostic in the future so that it can also run on top of or other Lisp dialects. For more updates follow . Wish me luck.

#lisp #verilog #systemverilog #vhdl #systemc #commonlisp #scheme #systemlisp

Last updated 3 years ago