#systemlisp now supports signals, these are objects whose values change over time and which emit posedge, negedge and edge events. In the picture below is a small example with some clock dividers. Still not ready to publish on github. Will do so when I'll have an asdf-able cl package and some interesting simulation examples. Next I will add support for exporting vcd waveform files and data types to 2-value and 4-value logic signals. #eda #verilog #vhdl #systemverilog #lisp #commonlisp
#systemlisp #eda #verilog #vhdl #systemverilog #lisp #commonlisp
#systemlisp now supports synchronization events. Next, I'll add support for signals. It's starting to take shape. Soon it will become a minimalistic HDL and I'll start implementing and simulating simple designs and testbenches with it. Stay tuned!
#lisp #commonlisp #verilog #vhdl #eda
#systemlisp #lisp #commonlisp #verilog #vhdl #eda
#systemlisp can simulate time! Next up, I'll add support for events, signals and expressions of signals. Moving forward slowly but steady. Will soon publish on github.
#lisp #commonlisp #eda
#systemlisp #lisp #commonlisp #eda
#Introduction Hello fellow Mastodonians! A few things about myself, I've worked most of my career in the semiconductor industry. I'm an expert in pre-silicon functional hardware verification using #SystemVerilog #UVM combined with other languages for higher level modeling such as #CPP #matlab #python. Right now I'm looking into #commonlisp to develop an EDA tool called #systemlisp. I'm also interested in #geopolitics and #astrodynamics. Big fan of Civilization 3 and Spaceflight Simulator games.
#astrodynamics #geopolitics #systemlisp #commonlisp #Python #matlab #cpp #uvm #systemverilog #Introduction
A pet project I'm working on right now is system-lisp, a #lisp dialect for hardware design, verification and virtual prototyping. It is meant to be a lisp-like alternative to #Verilog #SystemVerilog #VHDL #SystemC and Specman e. It will support digital, analog and mixed signal simulation as well as formal verification for digital designs and digital synthesis. You'll be able to design, simulate and verify your own hardware devices that can range from simple circuits, gadgets, appliances, cars planes or even spaceships. Right now I'm working on the discrete event simulation engine. I'm implementing it in #commonlisp but I intend to make it backend agnostic in the future so that it can also run on top of #scheme or other Lisp dialects. For more updates follow #systemlisp. Wish me luck.
#lisp #verilog #systemverilog #vhdl #systemc #commonlisp #scheme #systemlisp