James against the machine · @j
179 followers · 1472 posts · Server noise.j-w.au
IT'S ALL HAPPENING!
Open-source FPGA toolchain on macOS, in my good-friend-and-text-editor, Nova.
I'm still on the hunt for a better way (on a Mac) to synthesize SystemVerilog directly instead of converting it to Verilog first. If YOU know a way, lmkplskthx!
Nova is a fantastic, extensible tool from @cabel and his pals at @panic
#fpga #macDevelopment #yosys #verilog #systemVerilog #tangNano #panicNova #nova
#fpga #macdevelopment #yosys #verilog #systemverilog #tangnano #panicnova #nova
Didier Malenfant :analogue: · @didier
485 followers · 339 posts · Server malenfant.netJust updated the FAQ on the whole logic, reg, bit, wire and var mess in #Verilog
I really wish I’d had that handy when I first started…
#verilog #openfpga #fpga #systemverilog #openfpgatutorials
James against the machine · @j
173 followers · 1347 posts · Server noise.j-w.auDoes anyone into #electronics and #fpga have a recommendation for a toolchain and IDE for me, a newcomer to FPGAs?
I’ve been told I should “…learn #Verilog. Or better yet, #SystemVerilog!”
I'm using VSCode, Lushay Code, and #OSS-CAD-Suite. A good path?
• MacOS (M2, arm64 CPU) preferred
• Windows or NixOS available if there's a compelling reason!
• Dev boards: Tang Nano 9K; Tang Nano 20K; iCESugar
Thank you in advance for any tips/advice/pointers! (Boosts welcome if you know people who know!)
#electronics #fpga #verilog #systemverilog #oss
Didier Malenfant :analogue: · @didier
478 followers · 245 posts · Server malenfant.netQuartus: yeah don’t use X and Z values in your logic types because they doesn’t synthesize anyway on FPGAs.
Also Quartus: yeah don’t use the bit type, which should be the best type to use to represent that fact, because it only works for simulation.
Me: 🤪🔫
#openfpga #fpga #verilog #systemverilog
cpsask · @cpsask
71 followers · 815 posts · Server techhub.socialI have created a case where my input signal seems to have 2 drivers, seeing X’s, but everything I try to trace the signal drivers results in the simulator crashing. Ugh #simulation #systemverilog
Sigasi · @Sigasi
1 followers · 1 posts · Server noc.social👋 Hi, we’re Sigasi!
Our #Eclipse and #VSCode based #IDE helps #DigitalElectronics design & #Verification engineers deliver formally validated designs faster and more efficiently with instant code insights, intelligent completions, easy design navigation, zero-noise linting & refactoring.
Want to know more? Ask us anything!
#vunit #uvm #verilog #systemverilog #vhdl #hdl #verification #digitalelectronics #ide #vscode #Eclipse
Didier Malenfant :amiga: · @didier
296 followers · 864 posts · Server mastodon.gamedev.placeAnd here it is.... my first two entries into the #SystemVerilog FAQ over at the #OpenFPGA tutorials wiki.
https://github.com/DidierMalenfant/openFPGA-tutorials/wiki/System-Verilog-FAQ
#systemverilog #openfpga #analogpocket
Didier Malenfant :amiga: · @didier
294 followers · 863 posts · Server mastodon.gamedev.placeCurrently putting together the ultimate FAQ entry on logic vs reg vs wire vs tri in #SystemVerilog.
Wish me luck!!! 😂
RISC-V · @risc_v
707 followers · 2315 posts · Server noc.social
.@antmicro adapted the #OpenTitan configuration to fit into a small, accessible @XilinxInc #Artix7 A200T #FPGA, opening the path to synthesizing this #SystemVerilog design with the #opensource #Yosys/UHDM flow. Read more: https://riscv.org/blog/2023/04/adapting-opentitan-for-open-source-fpga-prototyping-and-tooling-development/ @google @chipsalliance
Original tweet : https://twitter.com/risc_v/status/1646134831858819072
#yosys #opensource #systemverilog #fpga #artix7 #opentitan
YosysHQ · @yosyshq
350 followers · 15 posts · Server fosstodon.org
Not convinced that Formal Verification is worth it? Try our ‘getting started with FV’ package.
Including 2 hours of tailored video support to make sure you start getting value fast.
* Industrial compliant language support includes #SystemVerilog, #VHDL & SVA
* Bundled verification IP includes #RISCV and AXI
* Access to all our tools including synthesis, #FPGA, and mutation coverage
Just 1800 euros for 3 months. To get started, book a call with our CSO Matt Venn.
#systemverilog #vhdl #riscv #fpga
Gray Beard · @graybeard85
13 followers · 88 posts · Server universeodon.com
#systemlisp now supports signals, these are objects whose values change over time and which emit posedge, negedge and edge events. In the picture below is a small example with some clock dividers. Still not ready to publish on github. Will do so when I'll have an asdf-able cl package and some interesting simulation examples. Next I will add support for exporting vcd waveform files and data types to 2-value and 4-value logic signals. #eda #verilog #vhdl #systemverilog #lisp #commonlisp
#systemlisp #eda #verilog #vhdl #systemverilog #lisp #commonlisp
David C. Norris · @dcnorris
148 followers · 328 posts · Server scicomm.xyz
Just finished a 1st reading of Sutherland's RTL Modeling book this morning! 🤓 #FPGA #SystemVerilog
Gray Beard · @graybeard85
0 followers · 4 posts · Server mstdn.social#Introduction Hello fellow Mastodonians! A few things about myself, I've worked most of my career in the semiconductor industry. I'm an expert in pre-silicon functional hardware verification using #SystemVerilog #UVM combined with other languages for higher level modeling such as #CPP #matlab #python. Right now I'm looking into #commonlisp to develop an EDA tool called #systemlisp. I'm also interested in #geopolitics and #astrodynamics. Big fan of Civilization 3 and Spaceflight Simulator games.
#astrodynamics #geopolitics #systemlisp #commonlisp #Python #matlab #cpp #uvm #systemverilog #Introduction
Gray Beard · @graybeard85
2 followers · 35 posts · Server universeodon.comA pet project I'm working on right now is system-lisp, a #lisp dialect for hardware design, verification and virtual prototyping. It is meant to be a lisp-like alternative to #Verilog #SystemVerilog #VHDL #SystemC and Specman e. It will support digital, analog and mixed signal simulation as well as formal verification for digital designs and digital synthesis. You'll be able to design, simulate and verify your own hardware devices that can range from simple circuits, gadgets, appliances, cars planes or even spaceships. Right now I'm working on the discrete event simulation engine. I'm implementing it in #commonlisp but I intend to make it backend agnostic in the future so that it can also run on top of #scheme or other Lisp dialects. For more updates follow #systemlisp. Wish me luck.
#lisp #verilog #systemverilog #vhdl #systemc #commonlisp #scheme #systemlisp
Dustin · @DigitalKrampus
7 followers · 90 posts · Server geekdom.socialTrying to figure out why I can’t pass a string and a formatted string into a task without the complete barfing. Seems like I should be able to but the compiler thinks one of the format arguments is a function call for some reason. Either that or I really need some sleep. #SystemVerilog #FPGA
iPostHuman · @william_cleveland
20 followers · 345 posts · Server mastodon.social
After Hours Engineering:
Welcome to a new journey exploring Systems on a Chip (SoC)s. In the series I'll focus mainly on two--possibly 4 SBCs--from Lone Dynamic's Machdyne range of boards: Schoko, Eis and Konfekt (not shown in video), and possibly the BlackiceEdge.
#fpga, #YosysHQ, #SoC, #SystemVerilog, #Machdyne, #RISC-V
.
🍺🍕📺
#fpga #yosyshq #soc #systemverilog #machdyne #risc
Am I? · @ami
118 followers · 813 posts · Server floss.social@mattgodbolt
I'm so sorry for you!
It might be too late for you to go to #VHDL (the coolest acronym ever, look it up), but at least save yourself and don't walk, run to #SystemVerilog.
Also, remember: HDLs used testbences long before C++ did
Skepickle · @skepickle
5 followers · 2 posts · Server tty0.socialFurther #intro tags: #cicd #jenkins #agile #linux #ansible #python #perl #tcl #git #c #cpp #regex #circuitdesign #electromancy #fpga #asic #soc #vhdl #verilog #systemverilog #uvm #scifi #fantasy #ttrpg #ttrpgs #dnd3e #boardgames
#intro #cicd #jenkins #agile #linux #ansible #python #perl #tcl #Git #c #cpp #regex #circuitdesign #electromancy #fpga #asic #soc #vhdl #verilog #systemverilog #uvm #scifi #fantasy #ttrpg #ttrpgs #dnd3e #boardgames
Skepickle · @skepickle
5 followers · 2 posts · Server tty0.socialFurther #intro tags: #cicd #jenkins #agile #linux #ansible #python #perl #tcl #git #c #cpp #regex #circuitdesign #electromancy #fpga #asic #soc #vhdl #verilog #systemverilog #uvm #scifi #fantasy #ttrpg #ttrpgs #dnd3e #boardgames
#intro #cicd #jenkins #agile #linux #ansible #python #perl #tcl #Git #c #cpp #regex #circuitdesign #electromancy #fpga #asic #soc #vhdl #verilog #systemverilog #uvm #scifi #fantasy #ttrpg #ttrpgs #dnd3e #boardgames
skepickle · @skepickle
1 followers · 17 posts · Server tty.socialFurther #intro tags: #devops #cicd #jenkins #agile #linux #ansible #python #perl #tcl #git #c #cpp #regex #circuitdesign #electromancy #fpga #asic #soc #vhdl #verilog #systemverilog #uvm #scifi #fantasy #ttrpg #ttrpgs #dnd3e #boardgames
#intro #devops #cicd #jenkins #agile #linux #ansible #python #perl #tcl #git #c #cpp #regex #circuitdesign #electromancy #fpga #asic #soc #vhdl #verilog #systemverilog #uvm #scifi #fantasy #ttrpg #ttrpgs #dnd3e #boardgames