Bloop. Just submitted my first chip design to #TinyTapeout using #Rust HDL! Amazing how accessible this stuff is thanks to the TT crew's fantastic design tools and documentation. https://gds-viewer.tinytapeout.com/?model=https://kpwebb.github.io/tt04-kpwebb-rusty-adder/tinytapeout.gds.gltf

My #tinytapeout design is coming along. Deadline is September 8th if you have something you want to submit.

Got my Risc-V cpu I’m making for #TinyTapeout 4 bit banging SPI to drive an LCD screen!

This is currently running on an ICE FPGA.

@gdd @cst1

#tinytapeout For some reason, the Verilator #linter used in the GitHub actions doesn't know about the Sky130 standard cells. However, I do directly instantiate some inverter cells in my ring oscillator TRNG design.

Consequence: the action fails because the linter raises an error.

Solution? Disable the linter.

#hardware #vlsi #badprogrammer #computerscience

@joeycastillo @matthewvenn

I think that would be a great project for #TinyTapeout!

My Risc-V (ish) CPU for #TinyTapeout 4 is alive!
Here on FPGA it is executing code from an FRAM over SPI. The program counts, and stores the count to the LED array on the FPGA dev board.

This tiny RiscV core is still in early stages, but I’ve got a decent proportion of the instructions done and just tried running a build using the #TinyTapeout flow but with 4x the area and it’s showing just over 25% utilisation.
Looking forward to seeing what options are available for the next Tiny Tapeout so I can work out what area I’ll have available!

Inevitably, I’ve started work on a #RiscV CPU.

I’m hoping to implement RV32E (the smallest subset of Risc-V) such that it might fit on a future #TinyTapeout (they plan to allow designs of different sizes - there’s no way 16 32-bit registers can fit in the current area, but with 4-6 times more area it would be plausible).

I made a tester for #TinyTapeout in MicroPython for Pico W.

First time I've tried to make a half decent web interface for something on Pico W using #pimoroni 's phew web framework, and the first time I've tried using PIO from MicroPython.

https://github.com/MichaelBell/TinyTapeoutTester

Got my #TinyTapeout design running on FPGA! The FPGA is also implementing the scanchain used to access individual designs (a modified version of it that works on fpga), to allow me to test in the same way I’m planning to drive the tiny Tapeout version.

It’s being driven by a Pico. Pressing the button emulates the 7 segment display that will be on the Tiny Tapeout PCB on the LED matrix on the ice fun board.

So in the last 3 weeks I've gone from "oo, #TinyTapeout sounds cool" to "isn't it a shame that the skywater 130 standard cell library doesn't have the particular flip-flop type that I want."

And on the way I've learned how to run analogue simulations so I can understand the timing of the ring oscillator I'm including in my design.

Hadn't done anything more low level than Verilog for an FPGA before - so this has been a fun journey!

This morning I seem to be learning more about github actions so I can improve the #TinyTapeout automated testing.

The GitHub CLI and especially
gh run view --job xxx --json
has helped understand what the heck is going on!

OK, I have got totally sidetracked on to #TinyTapeout. I think I can probably make the Hovalaag CPU work!

Feel slightly bad for the project I was originally intending to work on today, but important to remember that being able to just do something else that has grabbed your attention is the whole difference between "work" and "not work" 😀

1280x720 views of Mars over DVI from RP2040 can wait.

So #TinyTapeout 3. I just got the tools running on my laptop - maybe I should make a design...

I've made a calendar entry to watch about 10-15 minutes of VLSI design videos every Friday. Inspired by #tinytapeout to make more of an effort this year. https://www.youtube.com/playlist?list=PLZU5hLL_713x0_AV_rVbay0pWmED7992G

I submitted a design to TinyTapeout 2!

It is a simple 1-bit ALU drawn in Wokwi. No Verilog, just gates and wires: https://wokwi.com/projects/340318610245288530

The resulting layout can be viewed from within your browser: https://mole99.github.io/tt02-1bit-alu
As you can see, only a small area is actually in use for the handful of gates.

For those just getting started with ASIC design, TT is a great way to embark on your journey!

https://tinytapeout.com

#TinyTapeout #ASIC

Finished my entry for #tinytapeout 2 with a few hours to spare. It's not the most involved design - a replica of the classic TIL311 Hex display - but it was fun to design, and it'll be fun to play with when it comes in!
3D preview of the design: https://gds-viewer.tinytapeout.com/?model=http%3A%2F%2Frandyglenn.ca%2Ftt02-rglenn-hex-to-7-seg%2F%2Ftinytapeout.gds.gltf

@jangray Is it possible to do an efabless MPW design running all the tools in Github Actions like #TinyTapeout does, or will you have to set up all the tools on your own computer?

Last night I got the cocotb testbench for Aeonic working, and it uncovered a flaw in my SPI FRAM controller design. I didn't have time to redesign it, but I came up with a workaround, and got everything to pass simulation. Unfortunately the GDS flow reveals that Aeonic doesn't fit in #TinyTapeout 2, even thought the TT02 die area was increased. The report says my design has 160 D flip-flops, which is significantly more than I'd expected.

Last night I got the cocotb testbench for Aeonic working, and it uncovered a flaw in my SPI FRAM controller design. I didn't have time to redesign it, but I came up with a workaround, and got everything to pass simulation. Unfortunately the GDS flow reveals that Aeonic doesn't fit in #TinyTapeout 2, even thought the TT02 die area was increased. The report says my design has 160 D flip-flops, which is significantly more than I'd expected.