And the current routing status. Nine pages of schematics done. Three left to go.

#d2200 #datapoint #datapoint2200 #TTLProcessor

It's worth noting that this circuit functions for every opcode in the instruction register even if it's not a branch instruction.

It's only at the next stage that the processor examines whether the opcode is a jump, call or return and sends signals elsewhere to load an immediate address, push the program counter on the stack or pop a return address off the stack.

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Onto the A register. This uses a pair of 7495 4-bit parallel in, parallel out, shift registers. The top of the schematic is the input bus, the bottom is the two(!) output busses.

While the processor is 1-bit serial it can communicate with other devices over these parallel busses. I'm not sure why there are two output busses though.

On the PCB you're looking at the six chips on the right for the register and input and output buffers/inverters.

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And the address multiplexers. Data can be loaded into the address registers from 3 sources: the stack, the H and L registers or the temp address register. The multiplexers select the source.

The Temp Address Register is used when reading a call or jump inline address. These are the only instructions which take an immediate address. All other memory references have to go via the H and L registers.

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Another page of schematics done - the stack. An A4 page with few external connections and quite quick to route. :phew:

Z95 to 99 are the stack, Z100 the stack up/down counter. Z109 to Z112 are the address register/counters. Z101, 114 and 115 clock the memory until they match the address on A0 to A6. A7 to A10 are sent to the memory cards (top-right) for decoding on the board. Z79 decodes A11 and A12 to select a memory card.

#d2200 #kicad #TTLProcessor

All components placed - to match the positions on the original board. Still some fettling to do on the edge connectors.

I'm now finally realising how ridiculously large this board is. In a way which, for unknown reasons, I'd been completely oblivious to previously.

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I've copied the Decoder PCB to get the edges of the Processor PCB. I'm using a print out of the decoder PCB and the long edge dimension of the decoder board to work out the scale of the print out.

I can then measure and scale up from the print out.

I'll keep the old decoder components and silk screen for the moment to reuse dimensions and design standards.

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Now this is the dictionary definition of tedium. An entire page of power units for the logic gates.

Gaps are for chips with power connections on the main symbol. Not, BTW, the same as chips containing a single unit - there are several 8-input gates with one unit per chip but those still have a separate power unit.

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Adding footprints. No difficulty here. There's only 8 different footprints across the board: 3 for connectors; 2 for capacitors; 1 for resistors; and 2 for chips.

This was the early days of 74 series logic so only 14- and 16-pin packages in use.

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Adding a page of spare units, based off the table on the original schematics, but the design checker doesn't like it.

So, the original is hard to read, and I've not double checked what I've copied, but it clearly shows Z95 with some spare units. But Z95 is one of the RAM chips making up the stack. So this table is definitely error prone.

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Current status: proof reading the schematics. I’m following every connection and using highlighter pens to mark where I’ve been. And doing the same to my schematics. The assortment of colours helps to stop me getting muddled.

Thus probably counts as tedious but my brain enjoys this kind of task.

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With the #Datapoint memory board sent to the fab it's time for the most exciting part of the project: the processor board.

This is A3 sized and houses 117 ICs. I'll be adding as many blinkenlights as I can fit.

I intend to toot as much as I can about the design process. I think it should be ... ahem ... interesting.

But it won't be quick. I'll be fitting it around other projects, and it'll be a ton of work anyway.

#D2200 #Datapoint2200 #TTLProcessor

So, a memory access takes the same time as executing roughly 32 opcodes. If you're slow clocking the machine that would be a *very* slow and tedious process.

The processor generates the WORD_SELECT signal when it is rotating the memories to match an address on the address bus.

By listening to the signal the MCU will be able to fast-clock the machine during these periods and, effectively, skip them. 2/2

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The main purpose of this board is to divide the raw clock into ten steps. Eight of these clock memory, the other two are when the processor ‘does stuff’.

Each of these ten steps is then subdivided into four. This generates the two phase clock signals needed for the memory and other parts of the processor.

Since the machine has a one bit processor these signals also clock the internal shift registers, ALU, etc.

#datapoint 2200 #ttlprocessor

Last week I had a bout of ADHD and sat up until 3am turning the Decoder board into an actual PCB. A bit more work later and it's nearly complete. And looking rather lovely.

I'm adding a tonne of silk-screen to explain what the sections are doing, and the connectors too. Across the top are a bunch of LEDs to show the signals (more to come). And I'll add a controller to allow you to pause or slow-clock it.

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