Exploiting Hardware-Level Parallelism in the Manticore Hardware-Accelerated RTL Simulator https://hackaday.com/2023/05/10/exploiting-hardware-level-parallelism-in-the-manticore-hardware-accelerated-rtl-simulator/ #rtlsimulator #verilator #hardware #hdl
#rtlsimulator #verilator #hardware #hdl
If you’re using @panic ’s Nova to edit your Verilog files, you'll be happy to know that @tsalvo ‘s Verilog extension now supports linting too via verilator…
nova://extension/?id=com.tomsalvo.verilog&name=Verilog
#fpga #openfpga #verilog #nova #verilator
RT from Antmicro (@antmicro)
Co-simulate CPUs from RTL in #Verilator with @renodeio to run unmodified software in a deterministic simulation. Combine precise CPU models w/ reusable #opensource I/O components to build complete systems simulating e.g. #OpenTitan SoC w/ Ibex @risc_v CPU: https://antmicro.com/blog/2023/01/cpu-rtl-co-simulation-in-renode/
Original tweet : https://twitter.com/antmicro/status/1620833104154836992
#opentitan #opensource #verilator
Want To Play With FPGAs? Use Your Pico! https://hackaday.com/2022/12/31/want-to-play-with-fpgas-use-your-pico/ #RaspberryPiPico #fpgaemulation #RaspberryPi #emulation #verilator #verilog #pipico #rp2040 #FPGA #fpga
#RaspberryPiPico #fpgaemulation #RaspberryPi #emulation #verilator #verilog #pipico #rp2040 #fpga
Want To Play With FPGAs? Use Your Pico! - Ever want to play with an FPGA, but don’t have the hardware? Now, if you have one ... - https://hackaday.com/2022/12/31/want-to-play-with-fpgas-use-your-pico/ #raspberrypipico #fpgaemulation #raspberrypi #emulation #verilator #verilog #pipico #rp2040 #fpga
#fpga #rp2040 #pipico #verilog #verilator #emulation #raspberrypi #fpgaemulation #raspberrypipico
RT from fpga_kian (@splinedrive)
If you have no #fpga in your hand. just use your #riscv @mangopi_sbc to simulate your #verilog design with #verilator on it. It feels like a real fpga evalboard from form factor. Btw. it's simulate my new one cycle riscv cpu that executes raytracer code. #kianRiscV
[Video embedded in original tweet]
Original tweet : https://twitter.com/splinedrive/status/1578417325673705472
#fpga #riscv #verilog #verilator #kianRiscV
RT from Antmicro (@antmicro)
At this year's #ESSDERC - #ESSCIRC we will hold a talk on pre-silicon testing of the @GoogleOSS-sponsored @SkyWaterFoundry MPW designs using co-simulation with @renodeio and #Verilator. Visit https://www.esscirc-essderc2022.org/a-year-of-open-source-mpws to learn more. @efabless @risc_v @CHIPSAlliance
Original tweet : https://twitter.com/antmicro/status/1570769293930897413