IT'S ALL HAPPENING!

Open-source FPGA toolchain on macOS, in my good-friend-and-text-editor, Nova.

I'm still on the hunt for a better way (on a Mac) to synthesize SystemVerilog directly instead of converting it to Verilog first. If YOU know a way, lmkplskthx!

Nova is a fantastic, extensible tool from @cabel and his pals at @panic

#fpga #macDevelopment #yosys #verilog #systemVerilog #tangNano #panicNova #nova

Live now! Streaming for lolz. Let’s get some Analog Pocket coding on…

https://twitch.com/didiermalenfant

#ProjectFreedom #openFPGA #AnaloguePocket #FPGA #Verilog #IndieDev #GameDev #Twitch #Live

Just updated the FAQ on the whole logic, reg, bit, wire and var mess in #Verilog

I really wish I’d had that handy when I first started…

https://openfpgatutorials.org/docs/System-Verilog-FAQ

#OpenFPGA #FPGA #SystemVerilog #OpenFPGATutorials

QSPICE Picks Up Where LTSpice Left Us - [Mike Engelhardt] is a name that should be very familiar to the hardcore electroni... - https://hackaday.com/2023/08/25/qspice-picks-up-where-ltspice-left-us/ #mikeengelhardt #softwarehacks #mixed-mode #simulation #toolhacks #ltspice #verilog #analog #power #qorvo #spice #c

Live now for some more openFPGA dev shenanigans. Lots to catch up on and hopefully wrap up too today.

https://twitch.com/didiermalenfant

#ProjectFreedom #openFPGA #AnaloguePocket #FPGA #Verilog #IndieDev #GameDev #Twitch #Live

one CSP channel is used to transmit a request token, while the other is used to transmit results. All channels in the
resulting CSP program have at most a single reader and a single writer dynamically, so that execution
remains deterministic basic form of SASL does not include facilities for “primitive” operations that are
implemented in another language. Such primitives are not necessary to implement any pure statically-
allocated function, as these functions can be described directly in SASL. Calling functions that have
state or perform I/O could be problematic, as the optimisation and evaluation models may rely on the
pure functional nature of the language.
However, this does not stop the possibility of implementing external linkage (using the term from
software). Provided the primitive acts in a pure functional style, a call to an external function would look
just like a normal function call in the SASL source, with similar semantics. It would be synthesised to instantiation of a module defined directly in, for example, #Verilog. The primitive’s physical interface
would be highly dependent on the hardware “calling conventions” of the synthesis system, as would the
signalling for the top-level calling interface.

Does anyone into #electronics and #fpga have a recommendation for a toolchain and IDE for me, a newcomer to FPGAs?

I’ve been told I should “…learn #Verilog. Or better yet, #SystemVerilog!”

I'm using VSCode, Lushay Code, and #OSS-CAD-Suite. A good path?

• MacOS (M2, arm64 CPU) preferred
• Windows or NixOS available if there's a compelling reason!
• Dev boards: Tang Nano 9K; Tang Nano 20K; iCESugar

Thank you in advance for any tips/advice/pointers! (Boosts welcome if you know people who know!)

Quartus: yeah don’t use X and Z values in your logic types because they doesn’t synthesize anyway on FPGAs.

Also Quartus: yeah don’t use the bit type, which should be the best type to use to represent that fact, because it only works for simulation.

Me: 🤪🔫

#openFPGA #FPGA #Verilog #SystemVerilog

I’ll be live tonight 7pm CEST - 5pm UTC - 10am PST getting my signal tap on for my #openFPGA core on the #AnaloguePocket

https://twitch.com/didiermalenfant

By request we will do some :amiga: #Amiga stuff tomorrow night!

#ProjectFreedom #FPGA #Verilog #IndieDev #GameDev #Twitch

👋 Hi, we’re Sigasi!

Our #Eclipse and #VSCode based #IDE helps #DigitalElectronics design & #Verification engineers deliver formally validated designs faster and more efficiently with instant code insights, intelligent completions, easy design navigation, zero-noise linting & refactoring.

Want to know more? Ask us anything!

#HDL #VHDL #SystemVerilog #Verilog #UVM #VUnit

Last night’s shenanigans are now up on the tube…

https://www.youtube.com/watch?v=nS7LTRJbwFk&t

#ProjectFreedom #openFPGA #AnaloguePocket #FPGA #Verilog

Live now! Let’s get some Pocket coding on…

https://twitch.com/didiermalenfant

#ProjectFreedom #openFPGA #AnaloguePocket #FPGA #Verilog #IndieDev #GameDev #Twitch #Live

Going live tonight 7pm CEST/5pm UTC/10am PST for some Analogue Pocket live coding. Trying to wrap up the first version of the Flip gfx chip before we try to plug the CPU in.

https://twitch.com/didiermalenfant

#ProjectFreedom #openFPGA #AnaloguePocket #FPGA #Verilog #IndieDev #GameDev #Twitch

A Cycle-Accurate Sega Genesis with FPGA - The Field-Programmable Gate Array (FPGA) is a powerful tool that is becoming more ... - https://hackaday.com/2023/08/04/a-cycle-accurate-sega-genesis-with-fpga/ #retrocomputing #recreation #megadrive #decapped #genesis #verilog #fpga #sega

I’ve been a bit quiet recently, haven’t done much coding and spent my time reading the #verilog bible. Should be coming back strong next week…maybe with my first stream!

Another full day of debugging and understanding more and more about the ‘Right Way™’ to do things in #Verilog and…boom! 💥

My gfx chip is now working correctly based on the 4 registers it exposes. I still don't have a working CPU yet but this is using a little FSM to drive the chip.

This is so much fun…

#AnalogPocket #OpenFPGA #ProjectFreedom #pfx1

👾 New blog post: Stars and Sprites 👾

I think I now have enough #Verilog knowledge to get started on the real graphics chip for the pfx-1 console.

Wish me luck!

https://didier.malenfant.net/blog/projectfreedom/2023/05/25/stars-and-sprites.html

#AnalogPocket #OpenFPGA #FPGA #IndieDev #ProjectFreedom #pfx1

Recreating the Raspberry Pi RP2040 PIO interface in Verilog #RaspberryPi #Verilog #FPGA @lawriegriffiths

https://blog.adafruit.com/2023/05/23/recreating-the-raspberry-pi-rp2040-pio-interface-in-verilog-raspberrypi-verilog-fpga-lawriegriffiths/

#Adafruit

Recreating the Raspberry Pi RP2040 PIO interface in Verilog #RaspberryPi #Verilog #FPGA @lawriegriffiths https://blog.adafruit.com/?p=550001

Bringing The PIO To The FPGA https://hackaday.com/2023/05/22/bringing-the-pio-to-the-fpga/ #RaspberryPiPico #verilog #FPGA #PIO