New school semester, I'm gonna reload my machine for AMD #Xilinx #Vitis #Vivado so if I'm stretching out from Fedora for a bit do I pick Ubuntu LTS or Redhat 9.1 ? I'm not a fan of their latest shenanigans, but i'm just looking for a school tool now. Hoping I have good ARC 750 support. I tried ubuntu 23 but my custom partition config it missed the permissions on /home so got read only errors which I think I fixed. Not sold yet. Opinions?

Wow, #Vivado's code editor is utterly, utterly unusable. I've rarely seen such a bad editor. At least notepad.exe responds.

I got this wacky JTAG hat thing working such that #vivado can recognize one of my #FPGA boards.

Prior to the #Elmo takeover, :birdsite: was the perfect place to burn that endless #vivado waiting time. For about a decade I was associated with the #Dalek paradigm over there.

All of my :birdsite: friends were Daleks, and I got pretty good at typing with the Shift key depressed. Contrary to the stereotype, the :birdsite: Daleks were an extremely diverse bunch.

I miss them.

I need to start a list of things you can do while waiting for FPGA tools to synthesize and place and route a moderately large design.

Obviously burning time in the Fediverse is on it.

#xilinx #vivado

@h_thoreson Every mastodon server is allocated a person who deals with #xilinx #fpga boards. That person's role is to warn others of the time wasting nightmare that is #vivado.

@violator @h_thoreson Where can I buy this plastic bubble of which you speak? #vivado

Any #Vivado users here? Is it possible that the IP Core using AXI-Stream are buggy as hell?

* AXI4-Stream Broadcaster with a N width input and two outputs seems to set the width to 2*N on either output in the GUI, no matter if I set it manually.
* Connecting to a Slice with M width input only works from first output. But it also tells me I could connect m_axis_tvalid[1:0] which is not width M...

🤯 😩

#fpga #xilinx

#vivado me rend fou
«
[Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port

adc_clk_p_i

can not be placed on PACKAGE_PIN U18 because the PACKAGE_PIN is occupied by port

adc_clk_p_i
»

Comment voulez vous éradiquer la violence dans le monde après ça.

#fpga 's are truly amazing. So much to unpack with these. Zybo z7 is a nice solid dev platform, just remember when all else fails ditch USB power and go full wall-wort :) #xilinx #vhdl #vivado

#fpga 's are truly amazing. So much to unpack with these. Zybo z7 is a nice solid dev platform, just remember when all else fails ditch USB power and go full wall-wort :) #xilinx #vhdl #vivado